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flex36 tm 3.3v 32k/64k/128k/256k x 36 synchronous dual-port ram cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-06070 rev. *d revised june 24, 2004 features ? true dual-ported memory cells that allow simultaneous access of the same memory location ? synchronous pipelined operation ? organization of 1-mbit, 2-mbit, 4-mbit and 9-mbit devices ? pipelined output mode allows fast operation ? 0.18-micron cmos for optimum speed and power ? high-speed clock to data access ? 3.3v low power ? active as low as 225 ma (typ) ? standby as low as 55 ma (typ) ? mailbox function for message passing ? global master reset ? separate byte enables on both ports ? commercial and industrial temperature ranges ? ieee 1149.1-compatible jtag boundary scan ? 172-ball fbga (1 mm pitch) (15 mm 15 mm) ? 176-pin tqfp (24 mm 24 mm 1.4 mm) ? counter wrap around control ? internal mask register controls counter wrap-around ? counter-interrupt flags to indicate wrap-around ? memory block retransmit operation ? counter readback on address lines ? mask register readback on address lines ? dual chip enables on both ports for easy depth expansion functional description the flex36 family includes 1m, 2m, 4m and 9m pipelined, synchronous, true dual-port stat ic rams that are high-speed, low-power 3.3v cmos. two ports are provided, permitting independent, simultaneous access to any location in memory. the result of writing to the same location by more than one port at the same time is undefined. registers on control, address, and data lines allow for minimal set-up and hold time. during a read operation, data is registered for decreased cycle time. each port contains a burst counter on the input address register. after externally loading the counter with the initial address, the counter will increment the address inter- nally (more details to follow). the internal write pulse width is independent of the duration of the r/w input signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce0 or low on ce1 for on e clock cycle will power down the internal circuitry to reduce the static power consumption. one cycle with chip enables asserted is required to reactivate the outputs. additional features include: r eadback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (cntint ) flags, readback of mask register value on address lines, retransmit functionality, inte rrupt flags for message passing, jtag for boundary scan, and asynchronous master reset (mrst ). the cy7c0853 device in this family has limited features. please see see ?address counter and mask register operations [10] ? on page 8. for details. table 1. product selection guide density 1-mbit (32k x 36) 2-mbit (64k x 36) 4-mbit (128k x 36) 9-mbit (256k x 36) part number cy7c0850v cy7c0851v cy7c0852v cy7c0853v max. speed (mhz) 167 167 167 133 max. access time - clock to data (ns) 4.0 4.0 4.0 4.7 typical operating current (ma) 225 225 225 270 package 176tqfp 172fbga 176tqfp 172fbga 176tqfp 172fbga 172fbga cy7c093794v cy7c093894v cy7c09289v cy7c09369v cy7c09379v cy7c09389v3.3v 64k/128k x 36 and 128k/256k x 18 synchronous dual-port ram
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 2 of 29 note: 1. , 9m device has 18 address bits, 4m device has 17 address bits, 2m device has 16 address bits, and 1m device has 15 address b its. logic block diagram [1] a 0l ?a 17l clk l ads l cnten l cntrst l true ram array 18 addr. read back cntint l mask register counter/ address register cnt/msk l address decode dual-ported interrupt logic int l reset logic jtag tdo tms tck tdi mrst dq 9l ?dq 17l dq 0l ?dq 8l i/o control 9 9 9 9 dq 18l ?dq 26l dq 27l ?dq 35l ce 0l ce 1l r/w l b0 l b1 l b2 l b3 l oe l a 0r ?a 17r clk r ads cnten cntrst r 18 addr. read back cntint r mask register counter/ address register cnt/msk r address decode interrupt logic int r dq 9r ?dq 17r dq 0r ?dq 8r i/o control 9 9 9 9 dq 18r ?dq 26r dq 27r ?dq 35r ce 0r ce 1r r/w r b0 r b1 r b2 r b3 r oe r mirror reg mirror reg
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 3 of 29 pin configurations 1 234567891011121314 a dq32l dq30l cntintl vss dq13l vdd dq11l dq11r vdd dq13r vss cntintr dq30r dq32r b a0l dq33l dq29l dq17l dq14l dq12l dq9l dq9r dq12r dq14r dq17r dq29r dq33r a0r c nc a1l dq31l dq27l intl dq15l dq10l dq10r dq15r intr dq27r dq31r a1r nc d a2l a3l dq35l dq34l dq28l dq16l vss vss dq16r dq28r dq34r dq35r a3r a2r e a4l a5l ce1l b0l vdd vss vdd vdd b0r ce1r a5r a4r f vdd a6l a7l b1l vdd vss b1r a7r a6r vdd g oel b2l b3l ce0l cy7c0850v cy7c0851v cy7c0852v ce0r b3r b2r oer h vss r/w la8lclkl clkr a8r r/w rvss j a9l a10l vss adsl vss vdd adsr mrst a10r a9r k a11l a12l a15l [2] cntrstl vdd vdd vss vdd cntrstr a15r [2] a12r a11r l cnt/mskl a13l cntenl dq26l dq25l dq19l vss vss dq19r dq25r dq26r cntenr a13r cnt/mskr m a16l [2] a14l dq22l dq18l tdi dq7l dq2l dq2r dq7r tck dq18r dq22r a14r a16r [2] n dq24l dq20l dq8l dq6l dq 5l dq3l dq0l dq0r dq3r dq5r dq6r dq 8r dq20r dq24r p dq23l dq21l tdo vss dq4l vdd dq1l dq1r vdd dq4r vss tms dq21r dq23r note: 2. for cy7c0851v, pins m1 and m14 are nc. for cy7c0850v, pins k3, k12 m1, and m14 are nc top view 172-ball bga
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 4 of 29 pin configurations (continued) 1234567891011121314 a dq32l dq30l nc vss dq13l vdd dq11l dq11r vdd dq13r vss nc dq30r dq32r b a0l dq33l dq29l dq17l dq14l dq12l dq9l dq9r dq12r dq14r dq17r dq29r dq33r a0r c a17l a1l dq31l dq27l intl dq15l dq10l dq10r dq15r intr dq27r dq31r a1r a17r d a2l a3l dq35l dq34l dq28l dq16l vss vss dq16r dq28r dq34r dq35r a3r a2r e a4l a5l vdd b0l vdd vss vdd vdd b0r vdd a5r a4r f vdd a6l a7l b1l vdd vss b1r a7r a6r vdd g oel b2l b3l vss cy7c0853v vss b3r b2r oer h vss r/w l a8l clkl clkr a8r r/w rvss j a9l a10l vss vss vss vdd vss mrst a10r a9r k a11l a12l a15l vdd vdd vdd vss vdd vdd a15r a12r a11r l vdd a13l vss dq26l dq25l dq19l vss vss dq19r dq25r dq26r vss a13r vdd m a16l a14l dq22l dq18l tdi dq7l dq2l dq2r dq7r tck dq18r dq22r a14r a16r n dq24l dq20l dq8l dq6l dq5l dq3l dq0l dq0r dq3r dq5r dq6r dq8r dq20r dq24r p dq23l dq21l tdo vss dq4l vdd dq1l dq1r vdd dq4r vss tms dq21r dq23r top view 172-ball bga
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 5 of 29 pin configurations (continued) 132 131 130 129 128 127 126 125 124 123 122 104 121 120 119 118 117 116 115 114 113 112 111 110 109 103 108 107 106 105 nc a 6r a 5r a 4r v dd v ss dq 35r dq 34r a 1r a 2r a 3r a 0r a 7r b 0r b 1r ce 1r b 2r b 3r oe r ce 0r v dd v dd v ss v ss r/w r clk r mrst ads r cnten r a 8r cntrst r cnt/msk r a 9r a 10r a 11r a 12r v ss v dd a 13r a 14r a 15r [2] a 16r [2] dq 24r dq 20r nc a 6l a 5l a 4l v dd v ss dq 35l dq 34l a 1l a 2l a 3l a 0l a 7l b 0l b 1l ce 1l b 2l b 3l oe l ce 0l v dd v dd v ss v ss r/w l clk l v ss ads l cnten l a 8l cntrst l cnt/msk l a 9l a 10l a 11l a 12l v ss v dd a 13l a 14l a 15l [2] a 16l [2] dq 24l dq 20l dq 33l dq 32l dq 31l v dd v ss dq 30l dq 28l dq 29l dq 27l int l cntint l dq 16l dq 15l dq 17l dq 14l dq 13l v ss v dd dq 12l dq 11l dq 10l dq 9l dq 9r dq 10r dq 11r dq 12r v dd v ss dq 13r dq 14r dq 17r dq 15r dq 16r cntint r int r dq 27r dq 29r dq 28r dq 30r v ss v dd dq 31r dq 32r dq 33r dq 26l dq 23l dq 22l v dd v ss dq 21l dq 25l dq 19l dq 18l tdi tdo dq 8l dq 7l dq 6l dq 5l dq 4l v ss v dd dq 3l dq 2l dq 1l dq 0l dq 0r dq 1r dq 2r dq 3r v dd v ss dq 4r dq 5r dq 6r dq 7r dq 8r tms tck dq 18r dq 19r dq 25r dq 21r v ss v dd dq 22r dq 23r dq 26r 102 91 101 100 99 98 97 96 90 95 94 93 92 89 1 2 3 4 5 6 7 8 9 10 11 29 12 13 14 15 16 17 18 19 20 21 22 23 24 30 25 26 27 28 31 42 32 33 34 35 36 37 43 38 39 40 41 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 cy7c0850v cy7c0851v cy7c0852v 176-pin thin quad flat pack (tqfp) top view
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 6 of 29 note: 3. these pins are not available for cy7c0853v device. pin definitions left port right port description a 0l ?a 17l [1] a 0r ?a 17r [1] address inputs . ads l [3] ads r [3] address strobe input . used as an address qualifier. this signal should be asserted low for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. ce0 l [3] ce0 r [3] active low chip enable input . ce1 l [3] ce1 r [3] active high chip enable input . clk l clk r clock signal . maximum clock input rate is f max . cnten l [3] cnten r [3] counter enable input . asserting this signal low incremen ts the burst address counter of its respective port on each rising edge of clk. the increment is disabled if ads or cntrst are asserted low. cntrst l [3] cntrst r [3] counter reset input . asserting this signal low resets to zero the unmasked portion of the burst address counter of its respective port. cntrst is not disabled by asserting ads or cnten . cnt/msk l [3] cnt/msk r [3] a ddress counter mask register enable input . asserting this signal low enables access to the mask register. when tied high, the mask register is not accessible and the address counter operations are enabled based on t he status of the counter control signals. dq 0l ?dq 35l dq 0r ?dq 35r data bus input/output . oe l oe r output enable input . this asynchronous signal must be asserted low to enable the dq data pins during read operations. int l int r mailbox interrupt flag output . the mailbox permits communications between ports. the upper two memory locations can be used for message passing. int l is asserted low when the right port writes to the mailbox location of t he left port, and vice versa. an interrupt to a port is deasserted high when it reads the contents of its mailbox. cntint l [3] cntint r [3] counter interrupt output . this pin is asserted low when the unmasked portion of the counter is incremented to all ?1s.? r/w l r/w r read/write enable input . assert this pin low to write to, or high to read from the dual port memory array. b 0l ?b 3l b 0r ?b 3r byte select inputs . asserting these signals enables read and write operations to the corresponding bytes of the memory array. mrst master reset input . mrst is an asynchronous input signal and affects both ports. asserting mrst low performs all of the reset functi ons as described in the text. a mrst operation is required at power-up. tms jtag test mode select input . it controls the advance of jtag tap state machine. state machine transitions occur on the rising edge of tck. tdi jtag test data input . data on the tdi input will be shifted serially into selected registers. tck jtag test clock input . tdo jtag test data output . tdo transitions occur on the fallin g edge of tck. tdo is normally three-stated except when captured data is shifted out of the jtag tap. v ss ground inputs . v dd power inputs .
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 7 of 29 master reset the flex36 family devices undergo a complete reset by taking its mrst input low. the mrst input can switch asynchronously to the clocks. the mrst initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). the mrst also forces the mailbox interrupt (int ) flags and the counter interrupt (cntint ) flags high. the mrst must be performed on the flex36 family devices after power-up. mailbox interrupts the upper two memory locations may be used for message passing and permit communications between ports. ta ble 2 shows the interrupt operation for both ports of cy7c0853v. the highest memory location, 3ffff is the mailbox for the right port and 3fffe is the mailbox for the left port. ta ble 2 shows that in order to set the int r flag, a write operation by the left port to address 3ffff will assert int r low. at least one byte has to be active for a write to generate an interrupt. a valid read of the 3ffff location by the right port will reset int r high. at least one byte has to be active in order for a read to reset the interrupt. when one port writes to the other port?s mailbox, the int of the port that the mailbox belongs to is asserted low. the int is reset when the ow ner (port) of the mailbox reads the contents of the mailbox. the interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). each port can read the other port?s mailbox without resetting the interrupt. and each port can write to its own mailbox without setting the interrupt. if an application does not require message passing, int pins should be left open. table 2. interrupt operation example [1, 4, 5, 6, 7] function left port right port r/w l ce l a 0 l ?17 l int l r/w r ce r a 0r?17r int r set right int r flag l l 3ffff x x x x l reset right int r flagxxxxhl3ffffh set left int l flag x x x l l l 3fffe x reset left int l flag h l 3fffe h x x x x table 3. address counter and counter-mask register control operation (any port) [8, 9] clk mrst cnt/msk cntrst ads cnten operation description x l x x x x master reset reset address counter to all 0s and mask register to all 1s. h h l x x counter reset reset counter unmasked portion to all 0s. h h h l l counter load load counter with external address value presented on address lines. h h h l h counter readback read out counter internal value on address lines. h h h h l counter increment internally increment address counter value. h h h h h counter hold constantly hold the address value for multiple clock cycles. h l l x x mask reset reset ma sk register to all 1s. h l h l l mask load load mask register with value presented on the address lines. h l h l h mask readback read out mask register value on address lines. h l h h x reserved operation undefined notes: 4. ce is internal signal. ce = low if ce 0 = low and ce 1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the clk and can be deasserted after that. data will be out after the following clk edge and will be three-stated after the next clk edge. 5. oe is ?don?t care? for mailbox operation. 6. at least one of b0 , b1 , b2 , or b3 must be low. 7. a16x is a nc for cy7c0851v, therefore the interrupt addresses are ffff and efff; a16x and a15x are nc for cy7c0850v, therefor e the interrupt addresses are 7fff and 6fff. 8. ?x? = ?don?t care,? ?h? = high, ?l? = low. 9. counter operation and mask register operation is independent of chip enables.
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 8 of 29 address counter and mask register operations [10] this section describes the features only apply to cy7c0850v/cy7c0851v/cy7c0852v devices, but not to cy7c0853 device. each port of these devices has a program- mable burst address counter. the burst counter contains three registers: a counter register, a mask register, and a mirror register. the counter register contains the address used to access the ram array. it is changed only by the counter load, increment, counter reset, and by master reset (mrst ) operations. the mask register value affects the increment and counter reset operations by preventing the corresponding bits of the counter register from changing. it also affects the counter interrupt output (cntint ). the mask register is changed only by the mask load and mask reset operations, and by the mrst . the mask register defines the counting range of the counter register. it divides the counter register into two regions: zero or more ?0s? in the most significant bits define the masked region, one or more ?1s? in the least significant bits define the unmasked region. bit 0 may also be ?0,? masking the least significant counter bit and causing the counter to increment by two instead of one. the mirror register is used to reload the counter register on increment operations (see ?retransmit,? below). it always contains the value last loaded into the counter register, and is changed only by the counter load, and counter reset opera- tions, and by the mrst . table 3 summarizes the operation of these registers and the required input control signals. the mrst control signal is asynchronous. all the other control signals in ta ble 3 (cnt/msk , cntrst , ads , cnten ) are synchronized to the port?s clk. all these counter and mask operations are independent of the port?s chip enable inputs (ce0 and ce1). counter enable (cnten ) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. a port?s burst counter is loaded when the port?s address strobe (ads ) and cnten signals are low. when the port?s cnten is asserted and the ads is deasserted, the address counter will increm ent on each low to high transition of that port?s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array, and will loop back to the start. counter reset (cntrst ) is used to reset the unmasked portion of the burst counter to 0s. a counter-mask register is used to control the counter wrap. counter reset operation all unmasked bits of the counter and mirror registers are reset to ?0.? all masked bits remain unchanged. a mask reset followed by a counter reset will reset the counter and mirror registers to 00000, as will master reset (mrst ). counter load operation the address counter and mirror registers are both loaded with the address value presented at the address lines. counter readback operation the internal value of the counter register can be read out on the address lines. readback is pipelined; the address will be valid t ca2 after the next rising edge of the port?s clock. if address readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) will be three-stated. figure 1 shows a block diagram of the operation. counter increment operation once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addr essing the entire memory array. only the unmasked bits of the counter register are incre- mented. the corresponding bit in the mask register must be a ?1? for a counter bit to change. the counter register is incre- mented by 1 if the least signifi cant bit is unmasked, and by 2 if it is masked. if all unmasked bits are ?1,? the next increment will wrap the counter back to the initially loaded value. if an increment results in all the unma sked bits of the counter being ?1s,? a counter interrupt flag (cntint ) is asserted. the next increment will return the counter register to its initial value, which was stored in the mirror register. the counter address can instead be forced to loop to 00000 by externally connecting cntint to cntrst . [11] an increment that results in one or more of the unmasked bits of the counter being ?0? will de-assert the counter interrupt flag. the example in figure 2 shows the counter mask r egister loaded with a mask value of 0003fh unmasking the first 6 bits with bit ?0? as the lsb and bit ?16? as the msb. the maximum value the mask register can be loaded with is 1ffffh. setting the mask register to this value allows the counter to access the entire memory space. the address counter is then loaded with an initial value of 8h. the base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. the counter address will start at address 8h. the counter will increment it s internal address value till it reaches the mask register value of 3fh. the counter wraps around the memory block to location 8h at the next count. cntint is issued when the counter reaches its maximum value. counter hold operation the value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. such operation is useful in applic ations where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. n o t es: 10. this section describes the cy7c0852v, which have 17 address bi ts and a maximum address value of 1ffff. the cy7c0851v has 16 address bits, register lengths of 16 bits, and a maximum address value of ffff. the cy7c0850v has 15 address bits, register lengths of 15 bits, and a maximum address value of 7ff f 11. cntint and cntrst specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 9 of 29 counter interrupt the counter interrupt (cntint ) is asserted low when an increment operation results in the unmasked portion of the counter register being all ?1s.? it is deasserted high when an increment operation results in any other value. it is also de-asserted by counter reset, counter load, mask reset and mask load operations, and by mrst . retransmit retransmit is a feature that allows the read of a block of memory more than once without the need to reload the initial address. this eliminates the ne ed for external logic to store and route data. it also reduces the complexity of the system design and saves board space. an internal ?mirror register? is used to store the initially loaded address counter value. when the counter unmasked portion reaches its maximum value set by the mask register, it wraps ba ck to the initial value stored in this ?mirror register.? if the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the ?mirror register.? thus, the repeated access of the same data is allowed without the need for any external logic. mask reset operation the mask register is reset to all ?1s,? which unmasks every bit of the counter. master reset (mrst ) also resets the mask register to all ?1s.? mask load operation the mask register is loaded with the address value presented at the address lines. not all values permit correct increment operations. permitted values are of the form 2 n ? 1 or 2 n ? 2. from the most significant bit to the least significant bit, permitted values have zero or more ?0s,? one or more ?1s,? or one ?0.? thus 1ffff, 003fe, and 00001 are permitted values, but 1f0ff, 003fc, and 00000 are not. mask readback operation the internal value of the mask register can be read out on the address lines. readback is pipelined; the address will be valid t cm2 after the next rising edge of the port?s clock. if mask readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) will be three-stated. figure 1 shows a block diagram of the operation. counting by two when the least significant bit of the mask register is ?0,? the counter increments by two. this may be used to connect the cy7c0850v/cy7c0851v/cy7c0852v as a 72-bit single port sram in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. this even-odd address scheme stores o ne half of the 72-bit data in even memory locations, and the other half in odd memory locations.
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 10 of 29 from mask register mirror counter address decode ram array wrap 1 0 increment logic 1 0 +1 +2 1 0 wrap detect from mask from counter to counter bit 0 wrap figure 1. counter, mask, and mirror logic block diagram [1] 17 17 17 17 17 1 0 load/increment cnt/msk cnten ads cntrst clk decode logic bidirectional address lines mask register counter/ address register from address lines to readback and address decode 17 17 mrst
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 11 of 29 ieee 1149.1 serial boundary scan (jtag) [13] the cy7c0850v/cy7c0851v/cy7c0852v/cy7c0853v incorporates an ieee 1149.1 serial boundary scan test access port (tap). the tap controller functions in a manner that does not conflict with the operatio n of other devices using 1149.1-compliant taps. the tap operates using jedec-standard 3.3v i/o logic levels. it is composed of three input connections and one output connection required by the test logic defined by the standard. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the devices, and may be performed while the devices are operating. an mrst must be performed on the devices after power-up. performing a pause/restart when a shift-dr pause-dr sh ift-dr is performed the scan chain will output the next bit in the chain twice. for example, if the value expected from the chain is 1010101, the device will output a 11010101. this extra bit will cause some testers to report an erroneous failure for the devices in a scan test. therefore the tester shoul d be configured to never enter the pause-dr state. . 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 h h l h 11 0s 1 0 1 0 1 01 00 xs 1 x 0 x 0 x0 11 xs 1 x 1 x 1 x1 00 xs 1 x 0 x 0 x0 masked address unmasked address mask register bit-0 address counter bit-0 cntint example: load counter-mask register = 3f load address counter = 8 max address register max + 1 address register figure 2. programmable counter-mask register operation [1, 12] table 4. identification register definitions instruction field value description revision number (31:28) 0h reserved for version number. cypress device id (27:12) c001h defines cypress part number for the cy7c0851v c002h defines cypress part number for the cy7c0852v and cy7c0853v c092h defines cypress part number for the cy7c0850v cypress jedec id (11:1) 034h allows unique ident ification of the dp family device vendor. id register presence (0) 1 indicates the presence of an id register. notes: 12. the ?x? in this diagram represents the counter upper bits. 13. boundary scan is ieee 1149.1-compatible. see ?performing a pause/restart? for deviation from strict 1149.1 compliance
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 12 of 29 table 5. scan registers sizes register name bit size instruction 4 bypass 1 identification 32 boundary scan n [14] table 6. instruction identification codes instruction code description extest 0000 captures the input/out put ring contents. places the bsr between the tdi and tdo. bypass 1111 places the byr between tdi and tdo. idcode 1011 loads the idr with the vendor id code and places t he register between tdi and tdo. highz 0111 places byr between tdi and tdo. forces all cy7c0851v/cy7c0852v/ cy7c0853v output driver s to a high-z state. clamp 0100 controls boundary to 1/0. places byr between tdi and tdo. sample/preload 1000 captures the input/output ring contents. places bsr between tdi and tdo. nbsrst 1100 resets the non-boundary scan logic. places byr between tdi and tdo. reserved all other codes other comb inations are reserved. do no t use other t han the above. note: 14. see details in the device bsdl files.
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 13 of 29 maximum ratings [15] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................ ?65 c to + 150 c ambient temperature with power applied............................................?55 c to + 125 c supply voltage to ground potential .............. ?0.5v to + 4.6v dc voltage applied to outputs in high-z state..........................?0.5v to v dd + 0.5v dc input voltage ............ .................. ?0.5v to v dd + 0.5v [16] output current into outputs (low)............................. 20 ma static discharge voltage......... .............. .............. ...... > 2000v (jedec jesd22-a114-2000b) latch-up current..................................................... > 200 ma operating range range ambient temperature v dd commercial 0 c to +70 c 3.3v 165 mv industrial ?40 c to +85 c 3.3v 165 mv electrical characteristics over the operating range parameter description -167 -133 -100 unit min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v dd = min., i oh = ?4.0 ma) 2.4 2.4 2.4 v v ol output low voltage (v dd = min., i ol = +4.0 ma) 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i oz output leakage current ?10 10 ?10 10 ?10 10 a i ix1 input leakage current except tdi, tms, mrst ?10 10 ?10 10 ?10 10 a i ix2 input leakage current tdi, tms, mrst ?0.1 1.0 ?0.1 1.0 ?0.1 1.0 ma i cc operating current for (v dd = max.,i out = 0 ma), outputs disabled cy7c0850v cy7c0851v cy7c0852v 225 300 225 300 ma cy7c0853v 270 400 200 310 i sb1 [18] standby current (both ports ttl level) ce l and ce r v ih , f = f max 90 115 90 115 90 115 ma i sb2 [18] standby current (one port ttl level) ce l | ce r v ih , f = f max 160 210 160 210 160 210 ma i sb3 [18] standby current (both ports cmos level) ce l and ce r v dd ? 0.2v, f = 0 55 75 55 75 55 75 ma i sb4 [18] standby current (one port cmos level) ce l | ce r v ih , f = f max 160 210 160 210 160 210 ma capacitance [17] part number parameter description test conditions max. unit cy7c0850v/7c0851v/ cy7c0852v c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v 13 pf c out output capacitance 10 pf cy7c0853v c in input capacitance 22 pf c out output capacitance 20 pf note: 15. the voltage on any input or i/o pin can not exceed the power pin during power-up. 16. pulse width < 20 ns. 17. c out also references c i/o 18. i sb1 , i sb2 , i sb3 and i sb4 are not applicable for cy7c0853v because it can not be powered down by using chip enable pins.
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 14 of 29 ac test load and waveforms switching characteristics over the operating range parameter description -167 -133 -100 unit cy7c0850v cy7c0851v cy7c0852v cy7c0850v cy7c0851v cy7c0852v cy7c0853v cy7c0853v min. max. min. max. min. max. min. max. f max2 maximum operating frequency 167 133 133 100 mhz t cyc2 clock cycle time 6.0 7.5 7.5 10.0 ns t ch2 clock high time 2.7 3.0 3.0 4.0 ns t cl2 clock low time 2.7 3.0 3.0 4.0 ns t r [19] clock rise time 2.0 2.0 2.0 3.0 ns t f [19] clock fall time 2.0 2.0 2.0 3.0 ns t sa address set-up time 2.3 2.5 2.5 3.0 ns t ha address hold time 0.6 0.6 0.6 0.6 ns t sb byte select set-up time 2.3 2.5 2.5 3.0 ns t hb byte select hold time 0.6 0.6 0.6 0.6 ns t sc chip enable set-up time 2.3 2.5 na na ns t hc chip enable hold time 0.6 0.6 na na ns t sw r/w set-up time 2.3 2.5 2.5 3.0 ns t hw r/w hold time 0.6 0.6 0.6 0.6 ns t sd input data set-up time 2.3 2.5 2.5 3.0 ns t hd input data hold time 0.6 0.6 0.6 0.6 ns t sad ads set-up time 2.3 2.5 na na ns t had ads hold time 0.6 0.6 na na ns t scn cnten set-up time 2.3 2.5 na na ns t hcn cnten hold time 0.6 0.6 na na ns t srst cntrst set-up time 2.3 2.5 na na ns t hrst cntrst hold time 0.6 0.6 na na ns t scm cnt/msk set-up time 2.3 2.5 na na ns t hcm cnt/msk hold time 0.6 0.6 na na ns notes: 19. except jtag signals (t r and t f < 10 ns [max.]). 20. this parameter is guaranteed by desi gn, but it is not production tested. 21. test conditions used are load 2. r1 = 590 ? r2 = 435 ? c = 5 pf (b) three-state delay (load 2) 90% 10% 3.0v vss 90% 10% <2ns <2ns all input pulses 3.3v v th = 1.5v r = 50 ? z 0 = 50 ? (a) normal load (load 1) c = 10 pf output output
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 15 of 29 t oe output enable to data valid 4.0 4.4 4.7 5.0 ns t olz [20, 21] oe to low z 0000ns t ohz [20, 21] oe to high z 0 4.0 0 4.4 0 4.7 0 5.0 ns t cd2 clock to data valid 4.0 4.4 4.7 5.0 ns t ca2 clock to counter address valid 4.0 4.4 na na ns t cm2 clock to mask register readback valid 4.0 4.4 na na ns t dc data output hold after clock high 1.0 1.0 1.0 1.0 ns t ckhz [20, 21] clock high to output high z 0 4.0 0 4.4 0 4.7 0 5.0 ns t cklz [20, 21] clock high to output low z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns t sint clock to int set time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns t rint clock to int reset time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns t scint clock to cntint set time 0.5 5.0 0.5 5.7 na na na na ns t rcint clock to cntint reset time 0.5 5.0 0.5 5.7 na na na na ns port to port delays t ccs clock to clock skew 5.2 6.0 6.0 8.0 ns master reset timing t rs master reset pulse width 7.0 7.5 7.5 10.0 ns t rss master reset set-up time 6.0 6.0 6.0 8.5 ns t rsr master reset recovery time 6.0 7.5 7.5 10.0 ns t rsf master reset to outputs inactive 6.0 6.5 6.5 8.0 ns t rscntint master reset to counter interrupt flag reset time 5.8 7.0 na na ns switching characteristics over the operatin g range (continued) parameter description -167 -133 -100 unit cy7c0850v cy7c0851v cy7c0852v cy7c0850v cy7c0851v cy7c0852v cy7c0853v cy7c0853v min. max. min. max. min. max. min. max.
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 16 of 29 jtag switching waveform jtag timing parameter description 167/133/100 unit min. max. f jtag maximum jtag tap controller frequency 10 mhz t tcyc tck clock cycle time 100 ns t th tck clock high time 40 ns t tl tck clock low time 40 ns t tmss tms set-up to tck clock rise 10 ns t tmsh tms hold after tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t tdih tdi hold after tck clock rise 10 ns t tdov tck clock low to tdo valid 30 ns t tdox tck clock low to tdo invalid 0 ns test clock test mode select tck tms test data-in tdi te s t d a ta - o u t tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 17 of 29 switching waveforms master reset read cycle [ 4, 22, 23, 24, 25] notes: 22. oe is asynchronously controlled; all other inputs (excluding mrst and jtag) are synchronous to the rising clock edge. 23. ads = cnten = low, and mrst = cntrst = cnt/msk = high. 24. the output is disabled (high-impedance state) by ce = v ih following the next rising edge of the clock. 25. addresses do not have to be accessed sequentially since ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. mrst t rsr t rs inactive active tms tdo int cntint t rsf t rss all address/ data lines all other inputs t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency b0 ?b3 t sb t hb
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 18 of 29 bank select read [26, 27] read-to-write -to-read (oe = low) [25, 28, 29, 30, 31] notes: 26. in this depth-expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress cy7c0851v/cy7c08 52v device from this data sheet. address (b1) = address (b2) . 27. ads = cnten = b0 ? b3 = oe = low; mrst = cntrst = cnt/msk = high. 28. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 29. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 30. ce 0 = oe = b0 ? b3 = low; ce 1 = r/w = cntrst = mrst = high. 31. ce 0 = b0 ? b3 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, since oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to three- state the i/o for the wr ite operation on the next ri sing edge of clk. switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd t cklz t cd2 no operation write read read clk ce r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+3 a n+4 q n q n+3
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 19 of 29 read-to-write -to-read (oe controlled) [25, 28, 30, 31] read with address counter advance [30] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 q n clk ce r/w address data in data out oe q n+4 t cd2 t sa t ha t ch2 t cl2 t cyc2 clk address a n counter hold read with counter t sad t had t scn t hcn t sad t had t scn t hcn q x?1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address ads cnten data out
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 20 of 29 write with address counter advance [31] switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal data in address t sa t ha cnten ads
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 21 of 29 counter reset [32, 33] notes: 32. ce 0 = b0 ? b3 = low; ce 1 = mrst = cnt/msk = high. 33. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) clk address internal cnten ads data in address cntrst r/w data out a n a m a p a x 0 1 a n a m a p q 1 q n q 0 d 0 t ch2 t cl2 t cyc2 t sa t ha t sw t hw t srst t hrst t sd t hd t cd2 t cd2 t cklz [45] reset address 0 counter write read address 0 address 1 read read address a n address a m read
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 22 of 29 readback state of address counter or mask register [34, 35, 36, 37] notes: 34. ce 0 = oe = b0 ? b3 = low; ce 1 = r/w = cntrst = mrst = high. 35. address in output mode. host must not be driving address bus after t cklz in next clock cycle. 36. address in input mode. host can drive address bus after t ckhz . 37. an * is the internal value of the address counter (or the mask register depending on the cnt/msk level) being read out on the address lines. switching waveforms (continued) cnten clk t ch2 t cl2 t cyc2 address ads a n q x-2 q x-1 q n t sa t ha t sad t had t scn t hcn load address external t cd2 internal address a n+1 a n+2 a n t ckhz data out a n* q n+3 q n+1 q n+2 a n+3 a n+4 t cklz t ca2 or t cm2 readback internal counter address increment external a 0 ?a 16
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 23 of 29 left_port (l_port) write to right_port (r_port) read [38, 39, 40] notes: 38. ce 0 = oe = ads = cnten = b0 ? b3 = low; ce 1 = cntrst = mrst = cnt/msk = high. 39. this timing is valid when one port is writing, and other port is reading the same location at the same time. if t ccs is violated, indeterm inate data will be read out. 40. if t ccs < minimum specified value, then r_po rt will read the most recent data (written by l_port) only (2 * t cyc2 + t cd2 ) after the rising edge of r_port's clock. if t ccs > minimum specified value, then r_port will read the most recent data (written by l_port) (t cyc2 + t cd2 ) after the rising edge of r_port's clock. switching waveforms (continued) t sa t ha t sw t hw t ch2 t cl2 t cyc2 clk l r/w l a n d n t ckhz t hd t sa a n t ha q n t dc t ccs t sd t cklz t ch2 t cl2 t cyc2 t cd2 l_port address l_port data in clk r r/w r r_port address r_port data out
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 24 of 29 counter interrup t and retransmit [41, 42, 43, 44, 45] notes: 41. ce 0 = oe = b0 ? b3 = low; ce 1 = r/w = cntrst = mrst = high. 42. cntint is always driven. 43. cntint goes low when the unmasked portion of the address counter is incremented to the maximum value. 44. the mask register assumed to have the value of 1ffffh. 45. retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. switching waveforms (continued) t ch2 t cl2 t cyc2 clk 1fffd 1ffff internal address last_loaded last_loaded +1 t hcm counter 1fffe cntint t scint t rcint 1fffc cnten ads cnt/msk t scm
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 25 of 29 mailbox interrupt timing [46, 47, 48, 49, 50] switching waveforms (continued) t ch2 t cl2 t cyc2 clk l t ch2 t cl2 t cyc2 clk r 3ffff t sa t ha a n+3 a n a n+1 a n+2 l_port address a m a m+4 a m+1 3ffff a m+3 r_port address int r t sa t ha t sint t rint table 7. read/write and enable operation (any port) [1, 8, 51, 52] inputs outputs operation oe clk ce 0 ce 1 r/w dq 0 ? dq 35 x h x x high-z deselected x x l x high-z deselected xlhld in write llhhd out read h x l h x high-z outputs disabled notes: 46. ce 0 = oe = ads = cnten = low; ce 1 = cntrst = mrst = cnt/msk = high. 47. address ?3ffff? is the mailbox location for r_port of a 9m device. 48. l_port is configured for write operation, and r_port is configured for read operation. 49. at least one byte enable (b0 ? b3 ) is required to be active during interrupt operations. 50. interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of th e read clock. 51. oe is an asynchronous input signal. 52. when ce changes state, deselection and read happen after one cycle of latency.
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 26 of 29 ordering information 256k 36 (9m) 3.3v synchronous cy7c0853v dual-port sram speed (mhz) ordering code package name package type operating range 133 CY7C0853V-133BBC bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0853v-133bbi bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) industrial 100 cy7c0853v-100bbc bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0853v-100bbi bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) industrial 128k 36 (4m) 3.3v synchronous cy7c0852v dual-port sram speed (mhz) ordering code package name package type operating range 167 cy7c0852v-167bbc bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0852v-167ac a176 176-pin flat pack 24 mm 24 mm (tqfp) commercial 133 cy7c0852v-133bbc bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0852v-133bbi bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) industrial cy7c0852v-133ac a176 176-pin flat pack 24 mm 24 mm (tqfp) commercial cy7c0852v-133ai a176 176-pin flat pack 24 mm 24 mm (tqfp) industrial 64k 36 (2m) 3.3v synchronous cy7c0851v dual-port sram speed (mhz) ordering code package name package type operating range 167 cy7c0851v-167bbc bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0851v-167ac a176 176-pin flat pack 24 mm 24 mm (tqfp) commercial 133 cy7c0851v-133bbc bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0851v-133bbi bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) industrial cy7c0851v-133ac a176 176-pin flat pack 24 mm 24 mm (tqfp) commercial cy7c0851v-133ai a176 176-pin flat pack 24 mm 24 mm (tqfp) industrial 32k 36 (1m) 3.3v synchronous cy7c0850v dual-port sram speed (mhz) ordering code package name package type operating range 167 cy7c0850v-167bbc bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0850v-167ac a176 176-pin flat pack 24 mm 24 mm (tqfp) commercial 133 cy7c0850v-133bbc bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) commercial cy7c0850v-133bbi bb172 172-ball grid array 15 mm 15 mm with 1.0 mm pitch (bga) industrial cy7c0850v-133ac a176 176-pin flat pack 24 mm 24 mm (tqfp) commercial cy7c0850v-133ai a176 176-pin flat pack 24 mm 24 mm (tqfp) industrial
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 27 of 29 package diagrams 51-85132-** 176-lead thin quad flat pack (24 24 1.4 mm) a176
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 28 of 29 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagrams (continued) 172-ball fbga (15 x 15 x 1.25 mm) bb172 51-85114-*b
cy7c0850v/cy7c0851v cy7c0852v/cy7c0853v document #: 38-06070 rev. *d page 29 of 29 document history page document title: cy7c0850v/cy7c0851v/cy7c0852v/cy7c0853v flex36 tm 3.3v 32k/64k/128k/256k x 36 synchro- nous dual-port ram document number: 38-06070 rev. ecn no. issue date orig. of change description of change ** 127809 08/04/03 spn this data sheet has been ex tracted from another data sheet: the 2m/4m/9m data sheet. the following changes have been made from the original as pertains to this device: updated capacitance values updated ?read-to-write-to-read (oe controlled)? waveform revised static discharge voltage corrected 0853 pins l3 and l12 added discussion of pause/restart for jtag boundary scan power up requirements added to maximum rati ngs information revise t cd2 , t oe , t ohz , t ckhz , t cklz for the cy7c0853v to 4.7 ns updated i cc numbers updated t ha , t hb , t hd for -100 speed separated out from the 4m data sheet added 133-mhz industrial device to ordering information table *a 210948 see ecn ydt changed mailbox addresses from 1fffe and 1ffff to 3fffe and 3ffff. *b 216190 see ecn ydt/dcon corrected revision of document. cms does not reflect this rev change *c 231996 see ecn ydt removed ?a particular port can write to a certain location while another port is reading that location.? from functional description. *d 238938 see ecn wwz merged 0853 (9mx36) with 0852 (4mx36) and 0851(2mx36), add 0850 (1m x36), to the datasheet. added product selection table. added jtag id code for 1m device. added note 14. updated boundry scan section section. updated function description for the merge and addition.

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